1. Field of the Invention
The present invention relates to phase-change memory devices, and more particularly, the present invention relates to a phase-change memory and method which include the state restoration of a phase-change cell.
2. Description of the Related Art
Phase change memory cell devices rely on phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The differing resistance values exhibited by the two phases are used to distinguish logic values of the memory cells. That is, an amorphous state exhibits a relatively high resistance, and a crystalline state exhibits a relatively low resistance.
Reference is made to FIG. 1, which schematically illustrates the phase transition of a phase change cell. The phase change cell is made up of top and bottom electrodes 101 and 102, a resistive heater 103 such as BEC, and a volume of phase change material 104 such as a chalcogenide alloy. The phase of a portion of the phase change material 104 is set by Joule heating of the material according to an amount of current passed through the resistive heater 103 via a transistor 105. To obtain an amorphous state (referred to as a “RESET” state), a relatively high write current pulse (“RESET pulse”) is passed through the phase change cell to melt a portion of the material 104 for a short period of time. The current is removed and the cell cools rapidly to below the melting point, which results in the portion of the material 104 having an amorphous phase. The melting point of chalcogenide, for example, is approximately 610° C. To obtain a crystalline state (referred to as a “SET” state), a lower current write pulse (“SET pulse”) is applied to the phase change cell for a longer period of time to heat the material 104 to below its melting point. This causes the amorphous portion of the material to re-crystallize to a crystalline phase that is maintained once the current is removed and the cell is rapidly cooled. For example, the re-crystallization temperature of chalcogenide is approximately 450° C.
FIG. 2 illustrates the change in temperature over time of a chalcogenide phase change cell material during the SET and RESET operations. As shown, the material is made amorphous during a rapid cooling (e.g., a few nanosecond) after being heated to above the melting temperature Tm. Crystallization occurs by heating the material below the melting point Tm and above the crystallization temperature Tx for a longer period of time (e.g., 50 nanoseconds or less).
FIG. 3 is a graph showing the V-I characteristics of a phase change memory cell. Again, the example shown illustrates the case of a chalcogenide alloy phase change material. In this example, the SET current region of 1.0 to 1.5 mA is for writing a crystalline state of the memory cell, and the RESET current region of 1.5 to 2.5 mA is for writing an amorphous state of the memory cell. As is apparent from FIG. 3, during a read operation, the differing resistance values of the amorphous and crystalline states can be readily distinguished by application of a low read voltage (e.g., less than 0.5 volts) below a given threshold voltage Vt. The threshold voltage Vt is the voltage above which the current of the cell material becomes the same for both the amorphous and crystalline states.
In a conventional phase-change random access memory (PRAM), the phase change cell operates as a non-volatile memory. That is, sufficiently high write currents are applied to maintain the amorphous and crystalline states of the phase-change material.
In the conventional amorphous write operation (i.e., the RESET operation), the phase change process of the phase change material is characterized by sequential nucleus formation and growth steps. The growth steps result in a large ratio between the RESET resistance and the SET resistance. For example, the RESET resistance may be several tens to hundreds times larger than the SET resistance. This advantageously provides a relatively large sensing margin and data retention time. Unfortunately, however, a high write current is needed to achieve both nucleus formation and growth, and the overall power consumption is large.
It would therefore be desirable to provide a phase-change memory device, such as a PRAM, which exhibits reduced power consumption.